Majority logic binary adder



April 22, 1969 R. aE'rTs 3,440,413

MAJORITY LOGIC BINARY ADDER Filed Nov. 17, 1965 Sheet 2 of 2 J: I so C Ql w u l2 FIG. 2 STAGEI STAGEZ STAGES 01 A1 B1 0P2 7 we F56. 3 7 L F-2100 10m 1 1 02 HQ I G2 I 105 |o5 L 7 l l L .l

45 c z jm n 3' 1- -1 ns l l 0 M50 I I I United States Patent 3,440,413MAJORliTY LOGllC BINARY ADDER Robert Betts, Vestal, N.Y., assignor toInternational Business Machines Corporation, Armonk, N.Y., a corporationof New York Filed Nov. 17, 1965, Ser. No. 508,215 Int. Cl. G06f 7/385US. Cl. 235-176 7 Claims ABSTRACT OF THE DISCLOSURE A majority logicbinary adder having a plurality of stages with each stage having a firstmajority circuit which responds to inputs A B and C and provides anoutput carry signal C to the next higher order stage, a majority circuitwhich responds to inputs A B C C and C and provides an output sum signalS and means coupling the output carry signal C as a double input to thesecond majority circuit.

This invention relates to an arithmetic device and more particularly toa binary adder.

Much development effort has been devoted in recent times to makingadders faster in operation and simple in construction. The ripple ofcarries from stage to stage in a parallel adder arrangement constitutesone source of delay in generating a final sum. This source of time delayhas been alleviated in part by the use of carry lookahead circuits, butany saving in time by this technique involves an increase in equipmentand a consequent increase in cost.

Accordingly, it is a feature of this invention to minimize the time forcarry ripple through a plurality of adder stages, yet provide anarrangement of adder stages which are simple in construction, fast inoperation, and less expensive to manufacture and maintain.

It is a feature of this invention to provide an improved adder the speedof which is in the order of 20 nanoseconds or less per adder stagewithout the use of carry lookahead circuits.

It is another feature of this invention to provide an improved adderarrangement which utilizes two majority circuits per stage, one togenerate a sum and the other to generate a carry to the next high orderstage.

It is a further feature of this invention to provide an adderarrangement with a plurality of adder stages wherein each stage includesimproved logic for determining a correct sum.

In one arrangement according to this invention an improved adderarrangement is provided which includes a plurality of stages with eachstage having two majority circuits. The first of the majority circuitshas three inputs and receives binary inputs A B and a carry input C andprovides an output signal representing a carry C to the higher orderstage. The second of the majority circuits has five'inp-uts and receivesbinary inputs A B and a carry input C on three of its inputs. The carryoutput C is supplied from the first majority circuit to the tworemaining inputs of the second majority circuit. The second majoritycircuit includes provision which in essence inverts the inputs C and Cto U and 6, The second majority circuit provides an output signal havinga polarity which represents the polarity of the majority of the inputsignals A B C 6 and G The second majority circuit may be viewedalternatively as a device which responds to the inputs C C to provide anoutput signal which has a polarity which is the inverse of the polarityof the majority of the input signals A B, and C except in the caseswhere A B and C are alike. The majority circuits are pulse operated, andin order to save time, the majority circuit which generates a sum in onestage is pulse operated simultaneously with the majority circuit forgenerating a carry out in the next high order stage. The staggering oftimed pulses for this purpose may be accomplished by utilizing atransmission line to provide pulses of the appropriate polarity andtiming relationship.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawlllgS.

FIGURE 1 is a block schematic of an adder arrangement according to thisinvention.

FIGURE 2 shows the use of adder stages with a transmission line.

FIGURE 3 illustrates in detail the adder stages shown in block form inFIGURE 1.

Reference is made to FIGURE 1 which illustrates a three stage adderarrangement constructed according to this invention, Stages 10, 11 and12 each include a three input majority (M3) circuit and a five inputmajority (M5) circuit. Stages 10, 11, and 12 include respective threeinput majority circuits 20 through 22 and respective five input majoritycircuits through 32. Carry input C to the stage 10 is a constantnegative signal, representing binary zero, which is applied on a line tothe majority circuits 20 and 30. Signals representing a binary input Aare applied on a line 41 to the majority circuits 20 and 30, and signalsrepresenting a binary input B are applied on a line 42 to the majoritycircuits 20' and 30. The majority circuit 20 has an output on a line 43which represents a carry C and this signal is supplied to two differentpoints in the majority circuit 30 as explained more fully hereinafter.The carry output signal on the line 43 is connected to the majoritycircuits 21 and 31 of the next higher order stage 11. The carry C is apositive signal representing a binary one whenever two or more of theinputs A B and C are positive signals representing binary ones. Theequation for expressing this logic is C =M (A B C which is depicted inthe drawing along the carry output line 43. The majority circuit 30 instage 10 establishes an output signal on a line 44 representing a sum SThe sum S is a binary one whenever three or more of the inputs A B C G 6are positive signals representing binary ones. The equation whichexpresses this logic is which is depicted in the drawing near the outputline 44. The stage 11 receives signals representing binary inputs A andB on respective lines and 51, and these signals are coupled to themajority circuits 21 and 31. The majority circuit 21 provides an outputsignal on a line 52 representing a carry C and the carry signal isconveyed on the line 52 to the majority circuits 22 and 3 2 of stage 12.The carry signal on the line 52 is coupled to two different points inthe majority circuit 31 in stage 11 as explained more fully hereinafter.The output of the majority circuit 31 is a signal on the line 53representing a sum S Stage 12 receives signals representing binaryinputs Ag and B which are conveyed along respective lines and 61 to themajority circuits 22 and 32. An output signal on the line 62 from themajority circuit 22 represents a carry C The carry C is connected to anext stage, not shown, if more stages are employed. Otherwise, the carrysignal C represents the highest order bit of the sum if no additionaladder stages are employed. The carry signal on the line 62 is conveyedto two different points in the majority circuit 32 as explained morefully herein- 3 after. The output of the majority circuit 32 is a signalwhich represents a sum S The three input majority circuits 20 through 22in respective stages through 12 determine the proper carry output inresponse to associated inputs A B and O A carry output C may beexpressed as follows:

It is readily seen from this equation that the carry C is a binary onewhenever any two or more of the quantities A B or C are 1. The majoritycircuits through 22 in stages 10 through 12 provide an output signalwhich is like the majority of the input signals, and it is readily seenthat the output signal properly represents the correct carry output tothe next high order stage.

The majority circuits through 32 in respective stages 10 through 12generate the correct sum in response to the associated inputs. The sum Smay be expressed as follows:

The quantity C in essence performs an inversion function in the fiveinput majority circuit in the stage where the carry output is generated,but the carry output signal does no cause an inversion function to takeplace in the five input majority circuit to which it is supplied in thenext higher order stage. For example, if the carry output signal fromthe majority circuit 20 in FIGURE 1 is a binary one, it is supplied as abinary one to the majority circuit 31 in stage 11. In stage 10, however,this carry signal of binary one is applied to the five input majoritycircuit 30 with the same effect as if two binary zeros Were applied tothe majority circuit 30. In essence the carry signal on the line 43 tothe majority circuit 30 causes an inversion of the signal representingthe majority of the inputs A B and C in all cases except the one casewhere A B and C are all alike. Alternatively, the majority circuit 30provides an output signal which has a polarity the same as the majorityof the input quantities A B C 6 6 where the input quantity C is invertedby the majority circuit 30. In order to demonstrate that the properbinary sum S is generated by a five input majority circuit according tothe logic expressed in Equation (2) above, the results for each usefulcombination of the signals C A B 6 1 6 S and C are illustrated inrespective columns 1 through 7 of the table below:

The majority circuits 20 through 22 and 30 through 32 in FIGURE 1 areoperated by pulse signals applied to input lines 70 through 75. Thepulses are staggered in time. Clock pulse 1 (CP is applied to the inputline 70. This clock pulse persists for the duration of the addoperation. The next clock pulse 0P is applied to the input line 71 ofthe majority circuit 30 of stage 10, and the clock pulse CP is appliedsimultaneously to the majority circuit 21 of stage 11. The clock pulseCP persists for the duration of the add operation. Clock pulse CP isapplied to the input line 73 of the majority circuit 31 in stage 11, andthis pulse is applied simultaneously to the input line 74 of themajority circuit 22 in stage 12. The last clock pulse C1 is applied tothe input line 75 or the majority circuit 32 in FIGURE 12. Each of theclock pulses CP through CR; persists until the sum signals S, through Sand C are stored in a storage device, not shown. As soon as the storageof the sum signals has been accomplished, the clock pulses CP throughCR; may be terminated. The polarity of the clock pulses as discussedmore fully hereinafter. One suitable arrangement for generating clockpulses having the proper polarity and timing relationship is illustratedin FIGURE 2.

Referring next to FIGURE 2, stages 10, 11 and 12 of FIGURE 1 are shownconnected to a transmission line. The transmission line may be any oneof various well known types, but it is illustrated simply as a pair ofparallel lines and 81. By appropriately tapping off of the paralleltransmission line, pulses of suitable polarity and of the proper timingrelationship may be obtained. It is seen that the adder arrangement ofthis invention is qsasi-asynchronous, and successive stages are tappedoff at appropriate points such that the delay from stage to stage isjust long enough to allow the inputs to each stage to provide the propersteering currents to the next stage. The time for a full parallel add isthe time necessary to propagate carry signals through N stages which isin the order of 20 nanoseconds or less per bit with present dayequipment. It is pointed out that FIGURE 2 is merely illustrative of theuse of a transmission line for pulse operation of the various adderstages, and it does not depict the actual points on the transmissionline from which the various stages are tapped. However, this technologyis well developed, and since it constitutes no part of this inventionper se, further elaboration is considered unnecessary. Many good textson this subject matter are available, and one is Pulse Technoques byMoskowitz and Racker, published by Prentice-Hall, Inc., 1951. Noteespecially Appendix III commencing on page 284.

Reference is made next to FIGURE 3 for a description of the details ofeach of the adder stages in FIGURE 1. Since all of the stages in FIGURE1 are of the same construction, a description of one stage sufiices foran understanding of the remaining stages. The stage 11 of FIG- URE 1 isarbitrarily shown in FIGURE 3. It illustrates the details of themajority circuits 21 and 31 which are illustrated in block form inFIGURE 1. The majority circuit 21 in :F-IGURE 3 has three resistors 100,102 and 103 connected between the respective inputs B A C and the nodepoint between tunnel diodes 104 and 105. The tunnel diode 104 is pulsedwith a positive signal through a terminal 106 simultaneously as thetunnel diode is pulsed with a negative signal through a terminal 107.When the tunnel diodes 104 and 105 are energized with respectivepositive and negative pulses simultaneously, they present a signal atthe node which has the same polarity as the majority of the inputs. Forexample, if a majority of the inputs have positive signals representingbinary ones, the output signal on the line 52 is a positive signalrepresenting that the carry C is a binary one. If a majority of theinputs A B C are negative signals representing binary Zeros, the outputsignal on the line 52 is a negative signal representing that the carry Cis a binary zero.

The majority circuit 31 in FIGURE 3 has resistors 110 through 112connected between respective inputs B A C and the node point of tunneldiodes 113 and 114. The tunnel diode 113 is energized with a positivepulse through a terminal 114, and this signal is supplied through aresistor 115 to the tunnel diode. The tunnel diode 114 is energized witha negative pulse through a terminal 116, and this signal is suppliedthrough a resistor 117 to the tunnel diode. The line 52 from themajority circuit 21 is connected through a resistor to the tunnel diode113 and through a resistor 131 to the tunnel diode 114. The currentrepresenting the carr signal on the line 52 is split and applied equallyto the side of each tunnel diode opposite their common junction. Inputsignals A B and C are applied through the resistors 110 through 112 tothe common junction between the tunnel diodes 113 and 114. The resistors110 through 112 have a resistance value R, and the resistors 130 and 131have resistance value R. The signal applied on the line 52 through theresistors 130 and 131 to the opposite sides of the tunnel diodesprovides an inverse steering current which eiTects an inversion of thepolarity of the majority of the signals A B and C for all cases except'when A B and C are all alike. Alternatively, the majority circuit 31 inFIGURE 3 may be viewed as one which inverts the polarity of the carrysignal quantity C to the quantity 6 and provides an output sum S whichhas a polarity the same as the polarity of the majority of thequantities A B C 6 and 6 Thus it is seen that the output signal on theline 53 from the majority circuit 31 in FIGURE 3 properly represents thesum S for all combinations of the inputs A B and C While the inventionhas been particularly shown and described with reference to a preferredembodiment thereof, it will be understood by those skilled in the artthat various changes in form and detail may be made therein withoutdeparting from the spirit and scope of the invention.

What is claimed is:

1. An adder arrangement having a plurality of adder stages with eachadder stage including:

first and second majority circuits each having a series circuitincluding a pair of diodes serially connected with a common pointtherebetween,

first means while supplies binary input signals A and B and a carryinput C to the common point of said first and second majority circuits,said first majority circuit responding to the input signals A B and C todevelop an output signal which represents a carry C second means whichsupplies the carry output signal C as an input to the next stage,

impedance means connected across the series circuit of said secondmajority circuit, and

third means for supplying the carry output signal C from said firstmajority circuit to the impedance means in said second majority circuit,said impedance means supplying the output signal C as a double input tosaid second majority circuit wherein each input signal C has the effectof the equivalent quantity (5 in said second majority circuit, saidsecond majority circuit having an output signal representing a sum S thepolarity of which is like the p olarity oi the majority of the signals AB C CX+1 and CX+1.

2. The apparatus of claim 1 wherein the first majority circuit and thesecond majority circuit respond to signals applied thereto and providean output signal after one unit of time delay, the carry signal C beingprovided one unit of time delay after the signals A B and C are appliedto the first majority circuit and the sum signal S being provided twounits of time delay after the signals A B and C are applied to thesecond majority circuit and a pulse generator coupled to the adderstages which operates the adder stages in succession and the firstmajority circuit of one stage and the second majority circuit of thepreceding stage are pulsed simultaneously.

3. The apparatus of claim 2 in which the pulse generator means includesa transmission line which provides pulses for operating the adderstages.

4. The apparatus of claim 2 in which the pulses from the pulse generatorare applied across the series circuit in the first and second majoritycircuits of each adder stage, and pulses of unlike polarity are appliedto opposite ends of the series circuit in the first and second majoritycircuits of each adder stage.

5. An adder arrangement having a plurality of adder stages with eachadder stage including:

first and second majority circuits each of which responds to inputsignals and one unit of time delay thereafter provides an output signaltherefrom,

first means which supplies binary input signals A and B and a carryinput C to said first and second majority circuits, said first majoritycircuit responding to the input signals A B and C to develop an outputsignal after one unit of time delay which represents a carry C secondmeans which supplies the carry output signal C as an input to the nextstage,

third means which supplies the carry output signal C as a double inputto said second majority circuit wherein each input signal C has theeffect of the equivalent quantity fi in said second majority circuit,said second majority circuit providing an output signal representing asum S the polarity of which is like the polarity of the majority of thequantities A B C 6 and 6 one unit of time delay after the signal C issupplied as an input thereto,

whereby the carry signal C in each adder stage is provided one unit oftime delay after the input signals A B and C are applied thereto and thesum signal S in each adder stage is provided two units of time delayafter the input signals A B and C are applied thereto.

6. An adder having a plurality of stages:

each stage including first and second majority circuits,

first means which supplies binary input signals A and B and a carryinput C to said first and second majority circuits, said first majoritycircuit responding to the input signals A B and C to develop an outputsignal which represents a carry C second means which supplies the carryoutput signal C as an input to the next stage,

third means which supplies the carry output signal C as a double inputto said second majority circuit wherein each input signal C has theefiect of the equivalent quantity 6 in the second majority circuit,

said first and second majority circuits each including a circuit havinga first terminal, a second terminal, and a pair of diodes connected inseries between the first and second terminals, said diodes having acommon point therebetween,

resistive means connected between each binary input signal A B and C ofthe first means and the common point of the diodes in the first andsecond majority circuits, resistive means connected between the commonpoint of the first majority circuit and the first terminal of the secondmajority circuit, resistive means connected between the common point ofthe first majority circuit and the second terminal of the secondmajority circuit,

said second majority circuit having an output signal from the commonpoint representing a sum S the polarity of which is like the majority ofthe binary signals A B C, 6 and 6 7. An adder having a plurality ofstages with each stage including:

first and second majority circuits,

first means which supplies binary input signals A and B and a carryinput O to said first and second majority circuits, said first majoritycircuit responding to the input signals A B and C to develop an outputsignal which represents a carry C second means which supplies the carryoutput signal C as an input to the next stage,

third means which supplies the carry output signal C as a double inputto said second majority circuit wherein each input signal C has theeffect of the 7 equivalent quantity 6 in said second majority circuit,said first and second majority circuits having a pair of diodesconnected in series with a common point therebetween, said input signalsA B and C being 5 connected to said common point,

said second means and said third means being connected to said commonpoint of said first majority circuit to obtain the carry output signal Cresistive means connected in series with said pair of diodes in series,and

said third means being connected to said resistive means,

'whereby said second majority circuit provides an output signalrepresenting a sum S the polarity of which is like the polarity of themajority of the signals A B C3, 6 +1 and 6 8 References Cited UNITEDSTATES PATENTS 2,999,637 9/1961 Curry 235-17S 3,113,206 12/1963 Harel235176 3,275,812 9/1966 Coates et a1 235-173 OTHER REFERENCES W. A.Sauer: How to Achieve Majority and Threshold Logic With Semiconductors,Nov. 29, 1963, pp. 23-25.

MALCOLM A. MORRISON, Primary Examiner.

DAVID H. MALZAHN, Assistant Examiner.

US. Cl. X.R.

